In recent years, with the development of digital technologies, electronic devices such as mobile information devices and information home appliances have been developed to have much more advanced functions. Demands therefore arise for a larger capacity of nonvolatile memory elements, reduction of power consumption for writing, a higher speed for a writing/reading time, and a longer duration.
It is said that attempt at more micro-fabricated flash memories using existing floating gates has a limit to satisfy such demands. On the other hand, in the case of a nonvolatile memory element (resistance-variable memory) in which a variable resistance layer is used as a material of a memory part, the memory element has a simple structure including the variable resistance elements. Such a nonvolatile memory element is expected to offer further micro-fabrication, a higher speed, and lower power consumption.
The use of a variable resistance layer as a material of a memory part allows a resistance value of the variable resistance layer to change from high resistance to low resistance or from low resistance to high resistance depending on applied electric pulses, for example. Here, it is necessary to clearly distinguish two values of the low and high resistance from each other, and to achieve stable, high-speed change between the low and high resistance to memorize the two values as a nonvolatile memory. Various techniques have conventionally been disclosed to achieve stability of such memory characteristics and to micro-fabricate the memory elements.
One of the conventional techniques is disclosed in Patent Reference 1 to provide a memory element that is a variable resistance element serving as a memory cell. The variable resistance element includes two electrodes and a memory layer sandwiched by the two electrodes. With the structure, a resistance value of the memory layer can be reversibly changed. FIG. 11 is a cross-sectional view of a structure of the conventional memory element.
As shown in FIG. 11, the memory elements are a plurality of variable resistance elements 10 arranged in an array to serve as memory cells. In each of the variable resistance element 10, a high resistance layer 2 and an ion source layer 3 are sandwiched by a lower electrode 1 and an upper electrode 4. The set of the high resistance layer 2 and the ion source layer 3 forms a memory layer into which data to be recorded onto the variable resistance element 10 of each memory cell is written.
Each of the variable resistance elements 10 is arranged above a corresponding one of MOS transistors 18 formed on a semiconductor substrate 11. Each of the MOS transistors 18 includes source/drain regions 13 and gate electrodes 14, which are formed in a region separated from other regions by element separating layers 12 in the semiconductor layer 11. The gate electrode 14 serves also as a word line that is one of address lines of the memory element.
One of the source/drain regions 13 in the MOS transistor 18 is electrically connected to the lower electrode 1 of the variable resistance element 10 via a plug layer 15, a metal line layer 16, and a plug layer 17. The other source/drain region 13 of the MOS transistor 18 is connected to the metal line layer 16 via the plug layer 15. The metal line layer 16 is connected to a bit line that is the other one of the address lines of the memory element.
Different voltages are applied between the lower electrode 1 and the upper electrode 4, respectively, to cause potentials having different polarities. Thereby, an ion source in the ion source layer 3 in the memory layer is moved to the high resistance layer 2. Or, the ion source is moved from the high resistance layer 2 to the upper electrode 4. With the structure, a resistance value of the variable resistance element 10 is changed from a high resistance state to a low resistance state or from a low resistance state to a high resistance state, in order to memorize data into the variable resistance element 10.
There is another disclosure of an example of a memory element made of a material (variable resistance material) different from that disclosed in Patent Reference 1. In the disclosure, a transition metal oxide made of two elements is used. For example, Patent Reference 2 discloses NiO, V2O5, ZnO, Nb2O5, TiO2, WO3, and CoO for variable change materials.